Service Chain
• Technology Platform
• Process/PDK
• IP Design/Service/Maturity
• Application Platform
• Design Support
• AE Support for Customer
• Reference Flow
• Tape Out/Assembly/Testing
Design Ecosystem
• IP Alliance
• EDA Alliance
• Design Service Alliance
• Chip Assembly/Testing
Technical Event
Chip Assembly/Testing

Design service Lab provide test chip engineer testing service based on wafer and package sort. The test chips include SOC, NVM memory/Library IP, high speed interface IP, Mixed signal and RF IP. The lab can also support DIP,COB, QFP quick package.

  • IP Testing
  • SoC Testing
  • Bonding Service
  • RF wafer level testing

For more information, please contact your account manager or login to SMIC NOW

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